`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   13:51:49 06/04/2015
// Design Name:   Mux2to1
// Module Name:   D:/Libraries/Documents/Ingenieria en computacion/Arquitectura Computadoras/TrabajoFinalArquitectura/trunk/Final-Mips/Mux2to1Test.v
// Project Name:  Final-Mips
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Mux2to1
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Mux2to1Test;

	// Inputs
	reg [31:0] Input1;
	reg [31:0] Input2;
	reg sel;

	// Outputs
	wire [31:0] Out;

	// Instantiate the Unit Under Test (UUT)
	Mux2to1 uut (
		.Input1(Input1), 
		.Input2(Input2), 
		.sel(sel), 
		.Out(Out)
	);

	initial begin
		// Initialize Inputs
		Input1 = 15;
		Input2 = 30;
		sel = 0;

		// Wait 100 ns for global reset to finish
		#100;
      #100;
		sel = 1;
		#100;
		Input1 = 45;
		#50;
		Input2 = 60;
		#100;
		sel = 0;
		

	end
      
endmodule

